Multiple finger off chip driver (OCD) with single level translator

ABSTRACT

A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the OCD to be varied to match the impedance of a driven load. A plurality of PFET and NFET finger selection devices are used to select various combinations of output FETS and ballast resistor finger combinations to drive an output signal at a desired impedance level. The ballast resistors are scaled in ohmic value to the size of the output finger it is connected to. In this configuration, a constant ratio of FET impedance to ballast resistance is maintained in each drive stage (finger). By selecting various combinations of fingers various driver impedances can be selected.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to off chip driver (OCD)circuits and, more particularly, to programmable variable impedance OCDcircuits.

[0003] 2. Description of the Related Art

[0004] In electrical systems, output drivers are used to driveinput/output (I/O) devices or similar loads. In order to have efficientpower transfer it is important that the impedance of the driver closelymatch the impedance of the load; the load comprising the impedance ofthe driven device as well as the impedance of the transmission line.Each output driver is set up with a certain voltage/impedance thatmatches the strength of the transmission line and I/O device beingdriven by that specific driver. Thus, I/O devices with a low drivestrength would need an output driver with a high impedance, and highstrength I/O devices require a low impedance driver. Since each outputdriver typically has only one impedance rating, an output driver drivinga load other than the one it is designed for would result in too much ortoo little of the strength needed.

[0005] High performance output driver circuits require careful controlof both current switching and output impedance characteristics. Theformer requirement, commonly referred to as dI/dt control, requiresswitching the driver on over a specified period of time, or switchingmultiple stages of the driver on in sequence. Such output currentcontrol techniques are necessary to minimize the on-chip inductive noisewhich occurs due to the large current requirements of the output drivercircuits during switching. The driver impedance requirements result in“programmable impedance” drivers whose output resistance is varied usingcomplicated digital controls. This impedance matching is necessary toavoid signal degradations due to bus reflections at high frequencies,where the output data bus acts as a transmission line.

[0006] As product cycle times decrease, the current control andprogrammable impedance design points for an output driver must becarefully considered to avoid limiting the performance of the driver.Variable impedance OCDs have become necessary as I/O bus architecturesevolve from 66 MHZ single data rate (SDR) to 133 MHZ and higher doubledata rate (DDR) systems.

[0007] Simple prior art programmable impedance OCDs simply involvedplacing several fixed impedance off-chip drivers in parallel where eachdriver is commonly referred to in the art as a “finger”. By enabling ordisabling a selected number of fingers, usually with a control word, thecombined impedance of the OCD varies. Several inefficiencies exist withthis approach, such as the need for multiple Level Translators (LT) fordata signals and control. For one thing, driver impedance needs tochange incrementally from a control word and span over a wide impedancerange. Further, impedance linearity over Vdq is difficult to preservedepending on the number of fingers selected. An ideal output driverhaving Vdq linearity would have the impedance characteristics of aresistor. That is, the current it supplies or sinks would be directlyproportional to the voltage across the DQ output pin. In such an idealdriver, Vdq=Rdq*Idq. However, practical prior art output drivers areconstructed from transistors, which have a linear and saturated range ofoperation. When the output transistor is biased in the linear region,the DQ current and voltage characteristics are substantially linear.However, at the edges of this linear range the transistor begins tosaturate and current does not change proportionally with voltage, andoutput impedance rises orders of magnitude. It is therefore desirablefor an OCD to have a predictably small percentage change in impedanceover its range of Vdq, hence a high degree of linearity. It is alsodesirable to have this percentage change in impedance constant,independent of the numbers of fingers selected. In other words, if a 2%change in impedance occurs with a 7-ohm setting, a 2% change ispreferred for a 17-ohm setting.

SUMMARY OF THE INVENTION

[0008] The present invention is directed to a multiple finger off chipdriver (OCD) having a single level translator for each of a plurality ofPFET fingers and NFET fingers which allow the impedance of the OCD to bevaried to match the impedance of a driven load. A VSS-VDD level DATAINinput signal is supplied to both a PFET level translator (shifter) andan NFET level translator. The PFET level translator translates theDATAIN signal to a VDDQ level and the NFET level translator translatesthe DATAIN signal to a VSSQ level. The level translators can compriseeither a single stage or dual stages. In the single stage DATAIN isstored in a first latch formed by pull-up PFET pull-up devices and NFETpull-down devices where the NFETs are sized to over power the PFETs.Hence, a DATAIN signal at a 1-volt high level is translated to a 3-voltVDDQ level because the drains of the PFETs are at 3-volt VDDQ. A TRIPinput signal performs an enable function which must be at a logicallow-level for the latch to accept DATAIN. The dual stage translatorworks much the same way as the single level translator described aboveto translate the VDD=1-volt DATAIN level to 3-volt VDDQ level. Inaddition, a VSS ground level is then translated to VSSQ ground levelthrough a second latch such that the output signal is referenced betweenVSSQ and VDDQ levels.

[0009] A plurality of PFET and NFET finger selection devices may be usedto select various combinations of output FETS and ballast resistorfinger combinations to drive the VDDQ-VSSQ output signal at a desiredimpedance level. The ballast resistors are scaled in ohmic value to thesize of the output finger it is connected to. In this configuration, aconstant ratio of FET impedance (as a function of FET width) to ballastresistance is maintained in each drive stage (finger). By selectingvarious combinations of fingers various driver impedances can beselected.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The foregoing and other objects, aspects and advantages will bebetter understood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

[0011]FIG. 1 is a circuit schematic of the programmable off-chip driver(OCD) circuit according to the present invention;

[0012]FIG. 2 is a circuit diagram of the output FETs and BallastResistor circuit;

[0013]FIG. 3 is a is a circuit diagram of the PFET level translators;

[0014]FIG. 4 is a diagram of the NFET level translators;

[0015]FIG. 5 is a diagram showing OCD PFET impedance curves for thevarious combination of finger selections; and

[0016]FIG. 6 is a diagram showing OCD NFET impedance curves for thevarious combination of finger selections.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

[0017] Referring now to the drawings, and more particularly to FIG. 1,there is shown a circuit schematic of the programmable off-chip driver(OCD) circuit according to the present invention generally referred towith reference numeral 10. The OCD 10 translates a data signal DATAIN 12to an output drive signal DQ 14 having a desired impedancecharacteristic. Since the input signal DATAIN 12 typically has a logicvoltage level different than that recognized by the device to be driven,level translators (shifters) are required. Here, a pair of leveltranslators are used comprising a PFET level translator 16 and an NFETlevel translator 18. For example, the logic levels of the input signalDATAIN 12 may be relative to VDD and ground, where VDD represents alogic “1” at 1.9 volts. This needs to be translated to a logic signalrelative to VDDQ and ground, where VDDQ represents a logic “1” at 3.3volts. Details of the PFET level translator 16 and an NFET leveltranslator 18 are given with reference to FIGS. 3 and 4, respectively.

[0018] Still referring to FIG. 1, the output 30 of the PFET leveltranslator 16 supplies a signal to common gate nodes of a plurality ofPFET restore devices 34. As shown, there are four PFET restore devices34, one for each pull-up finger connected between VDDQ and the PFET gatelines 40 ₀₋₃. The output 14, is held in tristate by holding the PFETgates, lines 40 ₀₋₃ at VDDQ, and by holding NFET gates 52 ₀₋₃ at VSSQ.When the level translators 16 and 18 are held in tristate position bytristate signal TRIP, the PFET level translator 16 outputs a VSS signalon line 30. This enables PFET restore devices 34, and drives PFET gatelines 40 ₀₋₃ to VDDQ. Similarly, in tristate condition NFET leveltranslator 18 outputs a VDDQ level which enables NFET restore devices 50and drives NFET gate lines 52 ₀₋₃ to VSSQ.

[0019] In an active operation TRIP signal is deactivated and DATAINsignal is translated to VDDQ for ‘1’ data type or to VSSQ level for a‘0’ data type on lines 30 and 42 respectively. PFET finger selectionlines 20 ₀₋₃ and NFET finger selection lines 22 ₀₋₃ are enabled ordisabled for a desired pull-up and pull-down output impedance. With ahigh state on a PFET selection device 38, a PFET gate 40 ₀₋₃ will beconnected to VSS when level translator output line 30 is at VDDQ throughpull-down device 36. An enabled PFET finger in Output FET/Ballastresistor group 24 drives output signal DQ 14, to VDDQ.

[0020] In a similar manner NFET selection lines 22 ₀₋₃ are enabled ordisabled for a desired pull-down impedance, and when NFET leveltranslator outputs a VSSQ level on line 42, a selected NFET gate line 52₀₋₃ is enabled via device 46 as it is connected to VDDQ through pull-updevice 48. Selected NFET fingers in OUTPUT FETs 24 drive the DQ output14 to VSSQ. When FET selection lines 20 and 22 are in their disabledstate this would leave corresponding PFET gate lines 40 and NFET gatelines 52 floating with neither a restore path or an enable pathconducting. Floating nodes are unpredictable so to insure operabilityand reliability, PFET clamps 26 and NFET clamps 28 are also decoded withsignals 20 ₀₋₃ and 22 ₀₋₃ respectively to clamp an unused output gate 40or 52 to its proper tristate level.

[0021]FIG. 2 is a circuit diagram of the output FETs and ballastresistor circuit 24. The ballast resistors (58, 60, 62, and 64) arescaled in ohmic value to the size of the output finger it is connectedto. For example, in FIG. 2, 72Ω, 36Ω, 18Ω, and 9Ω resistors areconnected to the four output NFET/PFET pairs, 56 ₀₋₃ and 54 ₀₋₃,respectively. It is a feature of this invention to pair an output devicewith a predetermined drive strength, or nominal-linear impedance with aresistor which is a predetermined fraction of that nominal-linear FETimpedance. In this configuration, a constant ratio of FET impedance toballast resistance is maintained in each drive stage (finger).Specifically, in this example, the FET impedance to ballast resistor isa constant value (i.e., FET width*resistor value=constant). In thisexample, the product is 8640 as shown in the table below: FET WIDTH (μm)x Resistor Value (Q) =Constant 960 9 8640 480 18 8640 240 36 8640 120 728640

[0022] Of course the above is by way of example only and many othercombinations of FET impedances, resistor values, and product constantsmay be chosen.

[0023] It is desirable to proportion the size of the output fingers (andtheir corresponding ballast resistor) in a binary progression. Thisallows impedance selection over a wide range and provides asubstantially constant change in impedance per step of change.

[0024] In the preferred embodiment, four sets of NFET pull-down and PFETpull-up devices are scaled in a binary progression of strength with eachhaving a proportional ballast resistor. With ballast resistor values of9, 18, 36 and 72 ohms, the output impedance of this driver can be easilychanged between 12-ohms to 100-ohms.

[0025]FIG. 3 is a circuit diagram of the PFET level translators 16.Incoming signal DATAIN is a data signal swinging between VSS and VDD ofsay 1-volt. DATAIN is stored in the latch formed by PFET devices 88 and90, and pull-down NFETs 80, 82, 84 and 86. The NFET pull down devicesare sized adequately to over power the PFET pull up devices 88 and 90.Hence, a DATAIN signal at a 1-volt high level is translated to a 3-voltVDDQ level because the drains of the PFETs are at 3-volt VDDQ. The TRIPinput performs an enable function which must be at a logical low-levelfor the latch to accept DATAIN. Inverters 68, 70, 72 and 74 form a delaychain to delay the latch reset to enhance data-hold time if necessary.Inverters 76 and 78 are used to alter the polarity of the input signalsfor the complement side of the latch. While the PFET translator 16 shownin FIG. 3 has been illustrated as a single stage, it is understood thatit could also be implemented as a 2-stage level translator as describedbelow for the case of the NFET level translator 18.

[0026]FIG. 4 is a 2-stage NFET level translator 18. A first latch isformed by FETS 130, 132, 110, 112, 114 and 116, with inverters 100, 102,104, 106 and 108 works much the same way as the single level translatordescribed above to translate the VDD=1-volt DATAIN level to 3-volt VDDQlevel. Next, the VSS ground level is translated to VSSQ ground levelthrough the second latch formed by FETs 126, 128, 118, 120, 122 and 124.With NFET devices 122 and 124 sources at VSSQ the logical low level getstranslated to VSSQ. Output signal OUT is now referenced between VSSQ andVDDQ levels.

[0027] In this system of two latches, the gate level of the controllinginputs are referenced to the source level of the latch control devices.In the first latch, signal DATAIN is referenced to VSS as are thesources of NFET control devices 110, 112, 116 and 114. In the secondlatch, the PFET control devices 126 and 128 have gate-to-source voltagereferenced to VDDQ. Hence, when a control device is in its off biascondition, noise on its source supply is also common to the gate leveland is rejected as common-mode noise. FETs 118 and 120 are used asspeed-up devices to enhance the response to DATAIN and TRIP inputs. Thisdirect coupling between the primary inputs DATAIN and TRIP to the secondlatch enhances response time because the propagation delay through thefirst latch is circumvented.

[0028]FIG. 5 is a diagram showing the PFET I/V impedance curvesaccording to the invention for the example when VDDQ=2.25 volts. Byselecting various combinations of fingers (20 ₁₋₃ from FIG. 1) variousdriver impedances can be selected. The fifteen (15) possible fingerselections are shown in the diagram plotted against exemplary 17Ω and34Ω target curves. Taken in conjunction with the FIG. 2, the values onthe left side of the diagram indicate the sum of the selected FETimpedances (54 ₁₋₃) combined with the sum of the associated ballastresistors (58-64) added in parallel. For example, if PFET finger (0) isselected, the associated I/V curve is influenced by the FET impedance120 and a ballast resistor value of 72Ω. If for example, PFET fingers(0, 1, 2, 3) are selected, the associated curve is influenced by FETimpedances expressed as a function of FET width (120 μm+240+480+960=1800μm) combined with ballast resistors (72∥36∥18∥9=4.8Ω). So for example,if the OCD was to have an output impedance of 17Ω, PFET fingers (0, 3)would be selected since between 1.25 V and 2.25 volts fingers (0, 3)best approximates 17Ω. Similarly, if the OCD was to have an outputimpedance of 34Ω, PFET finger (2) would be selected since between 1.25 Vand 2.25 volts finger (2) best approximates 34Ω.

[0029]FIG. 6 is a diagram showing the NFET I/V impedance curves whenVDDQ=2.25 volts, similar to above. By selecting various combinations offingers (22 ₁₋₃ from FIG. 1) various driver impedances can be selected.The fifteen (15) possible finger selections are shown also plottedagainst exemplary 17Ω and 34Ω target curves. Taken in conjunction withthe FIG. 2, the values on the left side of the diagram indicate the sumof the selected FET impedances (56 ₁₋₃) combined with the sum of theassociated ballast resistors (58-64) added in parallel just as above forthe case of the PFET I/V impedance curves. For example, if NFET finger(0) is selected, the associated I/V curve is influenced by the FETimpedance 120 and a ballast resistor value of 72Ω. If NFET fingers (0,1, 2, 3) are selected, the associated curve is influenced by FETimpedances (120 μm+240+480+960=1800 μm) combined with ballast resistors(72∥36∥18∥9=4.8Ω). So for example, if the OCD was to have an outputimpedance of 17Ω, PFET fingers (0, 1, 2) would be selected since between0 volts and 1.25 volts fingers (0, 1, 2) best approximates 17Ω.Similarly, if the OCD was to have an output impedance of 34Ω, PFETfingers (0, 1) would be selected since between 0 volts and 1.25 voltsfingers (0, 1) best approximates 34Ω.

[0030] While the invention has been described in terms of a singlepreferred embodiment, those skilled in the art will recognize that theinvention can be practiced with modification within the spirit and scopeof the appended claims.

We claim:
 1. An off chip driver device with adjustable output impedance,comprising: a plurality of fingers for receiving an input data signal; aplurality of finger selection devices each for selecting a correspondingfinger; and an output circuit comprising a transistor and ballastresistor for each of said plurality of fingers, wherein said ballastresistor has a value inversely proportional to an impedance value ofsaid transistor for each of said plurality of fingers.
 2. An off chipdriver device with adjustable output impedance as recited in claim 1wherein a multiplication product of said ballast resistor value and saidimpedance value of said transistor is a constant value for each of saidfingers.
 3. An off chip driver device with adjustable output impedanceas recited in claim 2 wherein selecting combinations of said fingerschanges an output impedance of said off chip driver.
 4. An off chipdriver device with adjustable output impedance as recited in claim 2wherein said plurality of fingers comprise a set of PFET fingers and acorresponding set of NFET fingers.
 5. An off chip driver device withadjustable output impedance as recited in claim 4 further comprising: asingle PFET level translator for translating said input data signal froma first voltage level to a second voltage level for said set of PFETfingers; and a single NFET level translator for translating said inputdata signal from said first voltage level to a third voltage level. 6.An off chip driver device with adjustable output impedance as recited inclaim 5 wherein said a single PFET level translator comprises a singlelatch circuit.
 7. An off chip driver device with adjustable outputimpedance as recited in claim 5 wherein said a single PFET leveltranslator comprises a dual latch circuit.
 8. An off chip driver devicewith adjustable output impedance as recited in claim 5 wherein said asingle NFET level translator comprises a single latch circuit.
 9. An offchip driver device with adjustable output impedance as recited in claim5 wherein said a single NFET level translator comprises a dual latchcircuit.
 10. An off chip driver device with adjustable output impedance,comprising: a plurality of pull-up fingers each comprising a first typetransistor switching in a corresponding ballast resistor; a plurality ofpull-down fingers each comprising a second type switching transistorswitching in said corresponding ballast resistors; wherein said ballastresistors for each pull-up and pull-down finger are scaled inverselyproportional to the strength of said corresponding first type switchingdevice and said second type switching device and have a constant ratiofor all fingers.
 11. An off chip driver device with adjustable outputimpedance as recited in claim 10 wherein said pull-up fingers and saidpull-down fingers are scaled according to a binary weighting.
 12. An offchip driver device with adjustable output impedance as recited in claim10, wherein an output voltage is greater than a voltage of an inputsignal to said off chip driver.
 13. The off chip driver as recited inclaim 12 further comprising: a first level translator for translatingthe voltage level of the input signal for said plurality of pull-upfingers; and a second level translator for translating said voltagelevel of the input signal for said plurality of pull-down fingers. 14.The off chip driver as recited in claim 12 wherein each of said firstand second level translators comprises at least one latch.
 15. The offchip driver as recited in claim 10 further comprising a clamping circuitfor clamping unselected fingers.
 16. An off chip driver device withadjustable output impedance, comprising: a PFET level translator and anNFET level translator for translating a voltage level of an inputsignal; a plurality of PFET finger restore devices receiving an outputfrom said PFET level translator; a plurality of NFET finger restoredevices receiving an output from said NFET level translator; a pluralityof PFET finger selection devices for selecting one or more PFET fingers;a plurality of NFET finger selection devices for selecting one or moreNFET fingers; clamps for clamping unselected PFET fingers and unselectedNFET fingers; and an output stage comprising a plurality of outputfingers each comprising: a PFET being selected by a corresponding one ofsaid PFET finger selection devices, and an NFET being selected by acorresponding one of said NFET finger selection devices; and a ballastresistor connected at a first end between said PFET and said NFET and ata second end to an output terminal of said off chip driver device,wherein a value of said ballast resistor has an inverse relationship toan impedance value of said PFET and said NFET.
 17. An off chip driverdevice with adjustable output impedance as recited in claim 16 wherein amultiplication product of said impedance value of either of said NFETand said PFET with said ballast resistor value is identical for all ofsaid output fingers.
 18. An off chip driver device with adjustableoutput impedance as recited in claim 16 wherein said PFET leveltranslator comprises at least one latch.
 19. An off chip driver devicewith adjustable output impedance as recited in claim 16 wherein saidNFET level translator comprises at least one latch.
 20. An off chipdriver device with adjustable output impedance as recited in claim 16wherein said NFET level translator comprises two latches.